The conductor 31 is, for example, poly-silicon (Si). A set of the memory cell array 10B, the row decoder module 15B, and the sense amplifier module 16B will be referred to as a plane PN2. The semiconductor and sensor markets for IoT are projected to be $114.2B in 2025 compared to $27.6B in 2015, with a CAGR of 15.3%. The address register 12 stores address information ADD which is received from the memory controller 2 by the semiconductor memory 1. As illustrated in FIG. 12 illustrates an example of a cross-sectional structure of the memory cell array 10 in the region corresponding to the dummy block DBLK in the lead region HA. The memory pillar MP is formed in a columnar shape extending in the Z direction, and penetrates through, for example, the conductors 22 to 24. In plan views, for better understanding of the views, hatching is added as appropriate. The contact C4 includes a conductor 49 and a spacer SP, and penetrates through, for example, the conductors 21B, 22, and 23. Most 3D NAND memory stacks are now two tiers high, which adds an additional concern of top tier to bottom tier misalignment. Each of a plurality of first pillars (for example, MP) penetrates through the stacked first conductors in the second region (for example, CA of PN1 in FIG. In FIG. 18 illustrates an example of a planar layout of the memory cell arrays 10A and 10B in a first modification example of the embodiment, and FIG. Similarly, the slit SHE separates the select gate lines SGDa, SGDb, and SGDc. 7 illustrates a cross-sectional view of the memory cell array 10 taken along the line VII-VII in FIG. Each of the conductors 21A and 21B is, for example, poly-silicon, and the conductors 21A and 21B are made of an identical material, and thus may be integrally formed. 9 illustrates an example of a cross-sectional structure of the memory cell array 10 in a region corresponding to the dummy block DBLK in the cell region CA. A plurality of conductors 24 respectively corresponding to the select gate lines SGDa, SGDb, and SGDc are provided, for example, in a stepped form in the same manner as in the lead region HA. 16, for example, the block groups BLKG adjacent to each other between the planes PN1 and PN2 are interposed between the region of the dummy steps provided on one side in the Y direction and the BL connection region BLtap provided on the other side in the Y direction. & Terms of Use. The conductor 25 is provided on the conductor 24 via an insulating layer. The conductor 47 is provided on the contact CS, that is, on the conductor 46. For example, in the lead region HA, end parts of the word lines WL may be formed in a step of one row, and may be formed in steps of three or more rows. This time and expense can be avoided using advanced process modeling techniques. FIG. For example, in the active block ABLK, an aggregate of a plurality of memory pillars MP provided between the slits SLT and SHE adjacent to each other corresponds to a single string unit SU. A columnar second contact is provided on one of the fourth conductors closest to the third conductor in the seventh region. Figure 2. 16 illustrates a plan view of an example of the memory cell array according to of the embodiment. In the semiconductor memory 1 according to the embodiment, in a structure in which two planes PN1 and PN2 are adjacent to each other, the conductor 21B in the plane PN1 is provided separate from the conductor 21B in the plane PN2. Therefore, the semiconductor memory 1 according to the embodiment can prevent an increase in the chip area of the semiconductor memory 1 having a plurality of planes. An insulating layer and the conductor 24 are alternately stacked on the conductor 23. In the structure of the memory cell array 10 described above, the number of conductors 23 is designed based on the number of word lines WL. The third stacked body includes a fifth conductor at a same layer level as the first conductor and adjacent to the first conductor via a third insulator and an alternating stack of fourth insulators and sixth conductors above the fifth conductor, in the fourth region. Yokohama, Japan, July 16, 2020 – Fujitsu Semiconductor Memory Solution Limited today announced a launch of 4Mbit FRAM * MB85RS4MTY, which has the largest density in FRAM products operating up to 125 . The core member 30 contains an insulator such as silicon dioxide (SiO2). The slit SHE contains an insulator such as silicon dioxide (SiO2). The BL connection region BLtap is a region in which a contact for electrically connecting the bit line BL connected to the NAND string NS to the sense amplifier module 16 disposed under the memory cell array 10 is formed. Figure 1. The term “connection” in the present specification indicates that elements are electrically connected to each other, and includes that the elements are electrically connected to each other via other elements. In this case, for example, the contact C3 penetrating through the insulating layer is provided in the BL connection region BLtap, and thus the bit line BL is electrically connected to a wiring under the memory cell array 10. The horizontal-direction slit SLT in the active block ABLK may or not separate the select gate line SGS. Jan-Peter Kleinhans & Dr. Nurzat Baisakova October 2020 The Semiconductor Value Chain 5 Introduction Semiconductors, such as memory chips and processors, are the backbone of modern society. The semiconductor RAMs are of broadly two types-static RAM and dynamic RAM. For example, in 2019, Sony semiconductor became a top 10 global semiconductor supplier just by producing camera image sensors. Fig 5: ALD thickness dependence and layer etch. Overall Configuration of Semiconductor Memory 1. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator (for example, SLT in FIG. Such a semiconductor device may include, for example, a memory card such as an SD™ card, or a solid state drive (SSD). This process variation capability, coupled with a built-in Structure Search/DRC capability, can result in identification of the minimum contact location areas on chip. FIG. The dummy steps are stepped portions formed when stepped portions of the lead region HA are processed. Each block group BLKG extends in the X direction, and the block groups BLKG0 to BLKG3 are arranged in the Y direction. There is an additional requirement to create a “slit” etch to separate neighboring memory cells. This application is based upon and claims the benefit of priority from Japanese Patent Application No. In addition to standalone memory chips, blocks of semiconductor memory are integral parts of many computer and data processing integrated circuits. 15 illustrates a cross-sectional view of an example of the memory cell array in a region including a dummy block and a peripheral region of a block group in the semiconductor memory according to the embodiment. The active block ABLK is the block BLK used to store data. Respective portions where the memory pillar MP intersects the plurality of conductors 24 function as the select transistors ST1a to ST1c. For example, a slit SHE extending in the X direction is disposed between the horizontal-direction slits SLT arranged in the Y direction. 16 illustrates a region DP1 in which the conductor 21B corresponding to the plane PN1 is provided and a region DP2 in which the conductor 21B corresponding to the plane PN2 is provided. Structure of memory cell array 10 in lead region HA. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. As illustrated in FIG. The corresponding conductors 40 and 41 may be connected to each other via a plurality of contacts, and different wirings may be connected to each other among a plurality of contacts. A slit used for a replacement process on the word line WL may also be used for a replacement process on the source line SL. The embodiment shows the semiconductor memory 1 having two planes (planes PN1 and PN2). Process complexity increased dramatically during the transition from a 2D to a 3D Flash memory structure, since the 3D structure requires a multi-tier pillar-etch operation. The conductor 23 is formed, for example, in a plate shape which spreads along the XY plane. The conductor 25 is formed, for example, in a linear shape extending in the Y direction, and is used as the bit line BL. The row decoder module 15 transmits the voltage applied to the signal line corresponding to the selected word line, to the selected word line in the selected block BLK. 11, the slit SHE in the active block ABLK is provided to separate the plurality of conductors 24 respectively corresponding to the select gate lines SGDa, SGDb, and SGDc in the lead region HA. The conductor 23 covers a side surface of the block insulating film 35. The fifth conductor is electrically insulated from the seventh conductor. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. In contrast, the slit SLT may be provided between planes adjacent to each other such that the conductors 21B of the planes adjacent to each other are separated from each other. Data is the most valuable resource in today’s digital economy. A single tier 3D NAND memory cell modeled with SEMulator3D. In the active block ABLK, for example, the horizontal-direction slit SLT which extends from the lead region HA to the C4 connection region C4tap in the X direction is provided in the region between the horizontal-direction slits SLT adjacent to each other. 5. He then spent five years at Epson Research and Development, working on high-speed/high-frequency device design and characterization. Specifically, the upper end of the slit SLT is placed in, for example, the layer between the layer including the upper end of the memory pillar MP and the layer in which the conductor 25 is provided. Alternatively, the semiconductor memory 1 may include three or more planes. Each of the memory cell arrays 10A and 10B includes, for example, block groups BLKG0 to BLKG3. Even in this case, in the semiconductor memory 1 in the second modification example, it is possible to achieve the same effect as in the embodiment by providing the source line separation region DPdiv in the same manner as in the embodiment. EEPROM I/F Features <Interface Selection> : Generally, serial EEPROMs utilize 3 types of interfaces - Microwire, SPI, and I2C. Sources of the select transistor ST2 in the identical block BLK are connected in common to a source line SL. Read only memory (ROM) is an example of nonvolatile memory. A spacer may be provided on a side surface of the columnar conductor provided in the contact CC. Each of a plurality of second pillars (for example, MP) penetrates through the stacked fourth conductors in the sixth region (for example, CA of PN2 in FIG. 10, in the region of the active block ABLK in the lead region HA, a plurality of conductors respectively corresponding to the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD have portions (terrace portions) not overlapping overlying conductors. 14 illustrates a cross-sectional view of the memory cell array 10 taken along the line XIV-XIV in FIG. 1 illustrates an example cross-sectional view of the disclosed semiconductor memory cell 10 called floating junction gate (FJG) memory device. Each of the memory cell arrays 10A and 10B includes a plurality of blocks BLK0 to BLKn (where n is an integer of 1 or greater). In the following, the region in which the conductor 21B of the plane PN1 and the conductor 21B of the plane PN2 are separated from each other will be referred to as a source line separation region DPdiv. The dummy block DBLK or the active block ABLK is provided in a region between the horizontal-direction slits SLT adjacent to each other among a plurality of slits SLT provided in the comb-shaped slit SLT and arranged in the Y direction. As illustrated in FIG. Market segmentation The global semiconductor memory IP market is categorized on the basis of its type, application, and regional demand. Kim & Stewart LLP- TMC (San Jose, CA, US), Click for automatic bibliography A single semiconductor device may be configured through a combination of the semiconductor memory 1 and the memory controller 2. The conductors 60 and 64 are, for example, poly-silicon, and the conductor 64 corresponds to the conductor 21B. In other words, in a plan view, the region in which the conductor 21B is provided includes the region in which the conductor 22 is provided. Prior to the introduction of DRAM, RAM was a well-known memory concept. The core member 30 is formed in a columnar shape extending in the Z direction. An upper surface of the contact CH is in contact with a single conductor 25, that is, a single bit line BL. Even in this case, in the semiconductor memory 1 in the first modification example, it is possible to achieve the same effect as in the embodiment by providing the source line separation region DPdiv in the same manner as in the embodiment. FIG. Specifically, for example, in a process of removing the sacrifice member 62, the conductor 64 can prevent a short circuit failure between the source line SL and the select gate line SGS which may occur when a region near the conductor 22 is etched via the region from which the sacrifice member 62 is removed. For example, each NAND string NS may be designed to have any number of memory cell transistors MT and select transistors ST1 and ST2. In a read operation, the sense amplifier module 16 determines data stored in a memory cell based on a voltage of a bit line, reads a determination result, and transmits the determination result to the memory controller 2 as the data DAT. The conductor 21B is provided on the conductor 21A, and the conductors 21A and 21B are electrically connected to each other. 2 illustrates an example of a circuit configuration of the memory cell array 10 of the semiconductor memory 1 according to the embodiment by extracting one block BLK from a plurality of blocks BLK in the memory cell array 10. For example, the microprocessor chips that run computers contain cache memory to store instructions awaiting execution. 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